The present invention relates to a method for forming interconnects on a semiconductor wafer or printed circuit board (PCB). More particularly, the present invention relates to a method for forming reinforced interconnects having a support structure therein to achieve a high stand-off.
Development of microelectronics packaging has been continually driven by the quest to reduce costs and achieve higher packaging density and improved performance while still maintaining or even improving circuit reliability. To meet these ends, a flip-chip bonding process, where a semiconductor chip is assembled face down on a substrate or circuit board, has become a popular choice in microelectronics packaging. Flip-chip bonding is advantageous because the space normally required for bump or connections within the chip is eliminated. In addition, flip-chips generally provide superior performance in high frequency applications.
A flip-chip assembly is typically fabricated in three stages: forming interconnects or bumps on a chip, attaching the bumped chip to a board or substrate, and filling the space remaining under the bumped chip with an electrically non-conductive material. There are many conventional methods of forming interconnects on a semiconductor wafer. One method includes forming a gold stud bump on a substrate with a wire bonder and forming a second stud bump thereon with solder to increase the interconnect stand-off.
Although in theory, additional stud bumps may be stacked in succession to obtain a high stand-off, the process is problematic. Firstly, the top surface of each stud bump is unlikely to be flat, thus making stacking difficult. Secondly, if a stud bump is formed over three or more stacked bumps, it is likely to collapse during formation. Therefore, the maximum number of stud bumps is limited and the stand-off height restricted to about 60 microns. With a low stand-off of about 60 microns, the bump is prone to shear strain arising from a mismatch in coefficients of thermal expansion (CTE) between the semiconductor chip and the wafer substrate. Excessive strain can cause bump fracture resulting in failure of the flip chip assembly.
Another method of forming interconnects involves providing an elongated pillar with a total stand-off height in the range of 80 to 120 microns formed from two elongated pillars. This method begins by first forming a layer of photo-resist on a flip-chip. Portions of the photo-resist layer may then be irradiated to form through holes in the layer. The holes are separately filled with copper followed by a solder to form an elongated pillar.
To fill the holes, the entire structure may first be placed in a copper bath and electroplated to deposit copper in the holes. Subsequently, the entire structure may be placed in a solder bath and electroplated to fill the remaining space in the holes with solder. The photo-resist layer is then removed by chemical baths to expose the elongated pillar. Reflow of the elongated pillar can then be carried out to connect the flip chip to a substrate.
Unfortunately, this process for forming interconnects is expensive and involves numerous chemical solutions, which generate chemical wastes. Another problem is that the stand-off of the pillar is limited by the thickness of the photo-resist layer. Although thickness of the photo-resist layer can be increased, doing so limits the pitch of the pillar. In practice, the openings in the photo-resist layer typically have a reverse conical shape, i.e., the openings taper towards a narrow end at the bond pads. Therefore, if a fine pitch is desired, the thickness of the photo-resist layer may be limited to about 80 microns. Hence, there is a tradeoff between a high stand-off and a fine pitch.
In view of the foregoing, it would be desirable to have a method for forming interconnects that is low cost and does not involve wet chemicals. In addition, it would be desirable to have a method that provides high stand-off and fine pitch.